|
[ Pobierz całość w formacie PDF ]
.2 1Figure 6.30INTRµP INTCIRQBUFFER TRANSCEIVERThe interrupt DATA BUSDATA BUSIRRTIRcircuitry.3IO DIRM/IO3 RECEIVER7 INTACONTROL BUS4D/ECONTROLLERREADW/R6 5RAM3.When the microprocessor accepts the interruption, it entersinto INTA cycles.These cycles produce the necessary signals(M/IO, D/E, and W/R = 0) to cause the bus controller toissue an INTA signal to the interrupt controller.These con-ditions also create the proper XDIR and T/R conditions fordata movement from the IPC to the microprocessor.4.Each I/O system must have a special program called an in-terrupt service routine.This program is specific to that sys-tem s function and operational needs.After the controllerinforms the microprocessor that an interrupt has occurred,it must produce an address to point the microprocessor tothe starting address of the service routine that correspondsto the level of interrupt being serviced.This pointing ad-dress (vector address) is located in a portion of RAM memo-ry called the vector table.These addresses are physicallylocated in the lowest 1KB (0 3FF) of RAM memory in thesystem, and contain the starting addresses of the variousservice routines.5.The interrupt controller places an 8-bit interrupt vectoraddress (nn) on the XD0 XD7 data pins.The nn value cor-responds to the priority of the interrupt being serviced.Themicroprocessor pushes the contents of its internal registerson a stack and latches the vector address bits during thistime.6.The microprocessor jumps to the address specified by thevector byte and loads a four-byte address.This address Chapter 6 System Boards417represents the beginning address of the service routine forthe interrupting device.The microprocessor services theinterrupting device until an End Of Interrupt (EOI) instruc-tion is encountered in the routine.7.The EOI command from the CPU will cause the interruptcontroller s ISR bit to be cleared at the end of the secondINTA cycle.This marks the end of the service routine.Themicroprocessor retrieves the contents of its internal registersfrom the stack and resumes its normal operation at the pointwhere it left off when the interrupt was accepted.Table 6.6 lists the interrupt vectors and functions used in PC-compatible computer systems.These vectors can also be used bysoftware designers to execute software interrupts in the system.Bydoing so, they can take over direct control of the system s I/Odevices.Table 6.6Interrupt vectors.Interrupt Function0 Divide by zero1 Single step2 Non-maskable interrupt (NMI)3 Break point instruction4 Overflow5 Print screen6,7 Reserved8 Time-of-day hardware interrupt (18.2/sec.)9 Keyboard hardware interruptA ReservedB,C Serial communications hardware interruptsD Fixed-disk hardware interruptE Disk hardware interruptcontinues A+ Certification Training Guide418Table 6.6 ContinuedInterrupt FunctionF Printer hardware interrupt10 Video I/O call1 1 Equipment check call12 Memory check call13 Disk I/O call14 RS232 I/O call15 (not used)16 Keyboard I/O call17 Printer I/O call18 ROM basic entry code19 Bootstrap loader1A Time of day call1B Get control on keyboard break1 C Get control on timer interrupt1D Pointer to video initialization table1E Pointer to disk parameter table1F Pointer to graphics character generator20 DOS program terminate21 DOS function call22 DOS terminate address23 DOS CTRL-BRK exit address24 DOS fatal error vector25 DOS absolute disk read26 DOS absolute disk write27 DOS terminate, fix in storage28-3F Reserved for DOS40-5F Reserved60-67 Reserved for user-software interrupts Chapter 6 System Boards419Interrupt Function68-7F (not used)80-85 Reserved by BASIC86-F0 Used by BASIC interpreter while runningF1-FF (not used)Objective Non-Maskable Interrupts (NMI)Two system board-based conditions will cause a non-maskableinterrupt (NMI) signal to be sent to the microprocessor.The firstcondition occurs when an active IO Channel Check (IOCHCK) in-put is received from an options adapter card located in one of theboard s expansion slots [ Pobierz caÅ‚ość w formacie PDF ] |
Archiwum
|